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Cache memory
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#	Item
811	Image processing with minimal energy Application to Visual Communication Systems ———————– Technical Report ———————– Add to Reading List Source URL: www.moivre.usherbrooke.ca Language: English - Date: 2013-01-29 10:45:43 Computer architecture Microprocessors CPU cache Cache Computer memory Multi-core processor Intel Core Power management CPU power dissipation Computer hardware Computing Central processing unit
812	Improving Memory Latency Aware Fetch Policies for SMT Processors Francisco J. Cazorla1 , Enrique Fernandez2 , Alex Ram´ırez1 , and Mateo Valero1 1 2 Add to Reading List Source URL: personals.ac.upc.edu Language: English - Date: 2005-05-12 12:36:37 Central processing unit Microprocessors Parallel computing Threads CPU cache Multithreading Instruction-level parallelism Branch predictor Multi-core processor Computing Computer architecture Computer hardware
813	Cache Performance in Vector Supercomputers L. I. Kontothanassisy R. A. Sugumarz G. J. Faanesz J. E. Smithx M. L. Scotty Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2011-03-27 20:19:05 CPU cache Dynamic random-access memory Cache Random-access memory Memory bandwidth Memory hierarchy Acumem SlowSpotter Computer memory Computer hardware Computing
814	Performance Characterization of a Quad Pentium Pro SMP Using OLTP Workloads1 Kimberly Keeton, David A. Patterson, Yong Qiang He+, Roger C. Raphael+, and Walter E. Baker# Computer Science Division Add to Reading List Source URL: www.hpl.hp.com Language: English* - Date: 2002-03-06 19:31:08 Computer engineering Computer memory CPU cache Cache Microprocessors Pentium Pro Microarchitecture Pentium Pentium II Computer hardware Computer architecture Central processing unit
815	High Performance Software Coherence for Current and Future Architectures1 LEONIDAS I. KONTOTHANASSIS AND MICHAEL L. SCOTT^ Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2004-06-20 01:32:34 Computer memory Cache coherency Distributed computing architecture CPU cache Cache coherence Non-Uniform Memory Access Cache Concurrent data structure Shared memory Computing Concurrent computing Parallel computing
816	Fourth Workshop on Scalable Shared Memory Multiprocessors, Chicago, IL, April 1994 Issues in Software Cache Coherence Leonidas I. Kontothanassis and Michael L. Scott Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2011-03-27 18:54:49 Cache coherency Computer memory Parallel computing Central processing unit Cache coherence CPU cache Shared memory Distributed shared memory Cache Computing Concurrent computing Computer architecture
817	Allocation Policy Analysis for Cache Coherence Protocols for STT-MRAM-based caches A THESIS SUBMITTED TO THE FACULTY OF THE GRADUATE SCHOOL OF THE UNIVERSITY OF MINNESOTA Add to Reading List Source URL: conservancy.umn.edu Language: English - Date: 2014-12-31 03:01:17 Cache coherency Non-volatile memory Magnetoresistive random access memory Spintronics CPU cache MESI protocol Random-access memory Cache coherence Nonvolatile BIOS memory Computer hardware Computing Computer memory
818	US Forest Service National Interagency Support Cache Optimization and Review Report Add to Reading List Source URL: www.fs.fed.us Language: English - Date: 2013-03-20 16:32:39 Computer memory Electronic engineering Computing CPU cache Cache No instruction set computing Computer hardware
819	A Practical Testing Framework for Isolating Hardware Timing Channels Jason Oberg∗ , Sarah Meiklejohn∗ , Timothy Sherwood† and Ryan Kastner∗ ∗ Computer Science and Engineering, University of California, San Die Add to Reading List Source URL: www0.cs.ucl.ac.uk Language: English - Date: 2014-09-03 04:47:31 Electronic engineering Information flow Information theory CPU cache Electronics Timing attack Advanced Encryption Standard Function Flip-flop Computer memory Mathematics Computer hardware
820	Operating System Benchmarking in the Wake of Lmbench: A Case Study of the Performance of NetBSD on the Intel x86 Architecture Aaron B. Brown Margo I. Seltzer Harvard University {abrown,margo}@eecs.harvard.edu Add to Reading List Source URL: www.eecs.harvard.edu Language: English - Date: 2009-09-06 12:29:23 CPU cache Pentium Pro P5 Memory bandwidth Cache Benchmark Dynamic random-access memory Alpha 21164 Loop nest optimization Computer memory Computer hardware Computing

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